Test your Verilog HDL...

Q. List out the difference between casex, casez and case statements?

Q. If a code having more than one $monitor does it work all the $monitors?

Q. Write a Verilog code for asynchronous reset D-Flip-Flop & synchronous reset D-Flip-Flop?

Q. Does delay can synthesizable if not can you give where do use?

Q. Do you know about User defined primitives?

Q. How do you generate clock in Verilog ?(write 2 or more logics)?

Q. List out the difference between casex, casez and case statements?

Q. If a code having more than one $monitor does it work all the $monitors?

Q. Write a Verilog code for asynchronous reset D-Flip-Flop & synchronous reset D-Flip-Flop?

Q. Does delay can synthesizable if not can you give where do use?

Q. Do you know about User defined primitives?

Q. How do you generate clock in Verilog ?(write 2 or more logics)?

Q. What is difference between force, freeze and deposit?

Q. What is the difference between reg and wire?

Q. Can we write assign inside procedural block (is it syntactically correct)?

Q. List out the differences between task and function?

Q. Difference between Asynchronous and Synchronous reset?

Q. How to you code it(Verilog)?

Q. Write a Verilog code for frequency 2 divider?

Q. Write a Verilog code for frequency 3 divider?(Use only single edges trigger mechanism)

Q. What is the difference between $display, $write and $monitor?

Q. List out the few differences between 1995 and 2001 Verilog standards?

Q. What is MCD in Verilog?

Q. What is the difference between transport delay and inertial delay?

Q. Is the following one is correct? If correct Why? (Reason)

            `timescale 1 ps/ 1 ns

Q. What values does the following operators return(===,==)?

Q. What are the differences between blocking and non-blocking assignments. Does always non-blocking assignment infer a Flip-Flop?

Q. In a following code which statement will work(WHy)?

       module logictest(input a,b,clk,output reg temp);

       always @(posedge clk)

       begin

        temp <= a&b;//-----------Statement 1

        temp <= a|b;//-----------Statement 2

       end

      endmodule

Q. Does delay can synthesizable if not can you give where do use?

Q. Do you know about User defined primitives?

Q. How do you generate clock in Verilog ?(write 2 or more logics)

Q. Does the following code infer a latch

always @ (b or c)

begin

a = 0;

if (b) begin

d = c;

end
Q. What is meant by latch inferring ,how do you avoid it in design?
Q.  How many times does the following repeat loop will execute? 

begin

a = 1;

repeat (a)

a= b + 1;

end 

Q. Is the following statement is correct?

       reg [-1:5] x; 

Q. how can you pass real values through ports? 

Q. Maximum how many number files can be opened using fopen?

Q. Is it possible to disable a function, task, named block?

Q. What is delta simulation time?

Q.  Difference between && and &, if any?

Q.  What is the difference between $finish and $stop ?

Q.  What are the timing controls in Verilog?

Q. What is $strobe in Verilog?