Clock Domains Crossing Issues

Clock Domain Crossing

In today’s complex system on chip (SoC) designs, different blocks are operating at different frequencies.if suppose a signal is travelling from one clock domain to another some problems are occur which are  setup and hold violation, metastability and unreliable data transfers(data loss, data in coherency), CDC may occur when a signal is travelling from one block to another block which are operating at same frequency and their phases are not same.

To avoid this CDC issues there are some methods to solve:

• Handshake Signaling method.
• Asynchronous FIFO.

Simple Verilog code for single bit Clock Domain Crossing:

module clk_2_cross ( rst_n,clk1, clk2,d_in, d_out);

input rst_n;

//--------------------------input clk1;

input clk2;

input  d_in;

output d_out;

reg [7:0] data_out_meta;

reg [7:0] data_out_reg;

reg [7:0] data_out_reg_r;

wire[7:0] data_out;

// Always block to Synchronize the signal

always @ (posedge clk2 or negedge rst_n)

begin

 if (! rst_n)

  begin

     d_in1 <= 'b0;

     d_in2 <= 'b0;

 end

else

begin

  d_in1 <= d_in;

  d_in2 <= d_in1;

end

assign d_out = d_in2;

end

endmodule

Above code infers the following digital circuit.

For More Knowledge on this topics go to the Following links

          http://www.eetimes.com/document.asp?doc_id=1279906

          http://www.asic-world.com/tidbits/clock_domain.html