Verilog Reserved Words (key words)...

always	: starts an always begin ... end sequential code block
and	: gate primitive
assign	: parallel continuous assignment
automatic	: a function attribute, basically reentrant and recursive
begin	: starts a block that ends with  end (no semicolon)
buf	: gate primitive, buffer
bufif0	: gate primitive, buffer if control==0
bufif1	: gate primitive, buffer if control==1
case	: starts a case statement
casex	: starts a case statement where x matches
casez	: starts a case statement where z matches
cell	: library, cell identifier, in configuration
cmos	: switch primitive, cmos
config	: starts a configuration
deassign	: stops the corresponding  assign  from accepting new values
default	: optional last clause in a case statement
defparam	: used to over-ride parameter values
design	: top level module, in configuration
disable	: a task or block
endmodule	: end of a module definition
endprimitive	: end of a primitive definition
endspecify	: end of a specify
endtable	: end of a table definition
endtask	: end of a task definition
event	: data type
for	: starts a for statement
force	: starts net or variable assignment
forever	: starts a loop statement
fork	: begin parallel execution of sequential code
function	: starts a function definition
generate	: starts a generate block
genvar	: defines a generate variable
highz0	: drive strength 0
highz1	: drive strength 0
if	: starts an  if  statement, if(condition) ...
incdir	: state dependent path declaration
include	: file path for library
initial	: Include the file inspection
inout	: starts an initial begin ... end sequential block
input	: declares a port name to be both input and output
instance	: declares a port name to be input
integer	: specify instance name, in configuration
join	: variable data type, 32 bit integer
large	: end of a parallel fork
liblist	: library search order for modules, in configuration
library	: location of modules, libraries and files
localparam	:  starts a local parameter statement, not over-ridden
macromodule	: same as module with possibly extra meanings
medium	: charge strength, 2, of trireg
module	: begin a module definition, also called a cell or component
nand	: gate primitive, nand
negedge	: event expression, negative edge
nmos	: switch primitive, nmos
nor	: gate primitive, nor
noshowcancelled	: no report trailing edge precedes leading edge, in specify
not	: gate primitive, not
notif0	: gate primitive, not if control==0
notif1	: gate primitive, not if control==1
or	: gate primitive, or
output	: declares a port name to be an output
parameter	: starts a parameter statement
pmos	: switch primitive, pmos
primitive	: event expression, positive edge
posedge	: starts the definition of a primitive module
pull0	: drive strength 5
pull1	: drive strength 5
pulldown	: gate primitive
pulsestyle_onevent	: glitch detection, in specify
real	: variable data type, implementation defined floating point
realtime	: variable data type, floating point time
reg	: variable data type, starts a declaration of name(s)
release	: release a forced net or variable assignment
remos	: switch primitive, remos
repeat	: starts a loop statement
rnmos	: switch primitive, rnmos
rpmos	: switch primitive, rpmos
rtran	: bidirectional switch primitive, rtran
rtranif0	: bidirectional switch primitive, rtranif0
rtranif1	: bidirectional switch primitive, rtranif1
scalared	: property of a vector type
showcancelled	: report trailing edge precedes leading edge, in specify
signed	: type modifier, reg signed
small	: charge strength, 1,  of trireg
specify	: starts a specify block
specparam	: starts a parameter statement for timing delays
strong0	: drive strength 6
strong1	: drive strength 6
supply0	: net data type, and drive strength 7
supply1	: net data type, and drive strength 7
table	: start a table definition in a primitive
task	: starts a task definition
time	: variable data type, 64 bit integer
tran	: bidirectional switch primitive, tran
tranif0	: bidirectional switch primitive, tranif0
tranif1	: bidirectional switch primitive, tranif1
tri	: net data type
tri0	: net data type, connected to VSS
tri1	: net data type, connected to VDD
triand	: net data type, tri state wired and
trior	: net data type, tri state wired or
trireg	: register data type associates capacitance to the net
unsigned	: type modifier, unsigned
use	: library, cell identifier, in configuration
vectored	: property of a vector type
wait	: starts a wait statement
wand	: net data type, wired and
weak0	: drive strength 3
weak1	: drive strength 3
while	: starts a sequential looping statement, while(condition)
wire	: net data type, a basic wire connection
wor	: net data type, wired or
xnor	: gate primitive, xnor not of exclusive or
xor	: gate primitive, xor exclusive or