Q. What is setup time and hold time?
Q. Implement logic gates(nand, nor, xor, xnor, and, or & not) using mux2:1?
Q. Implement logic gates(nand, nor, xor, xnor, and, or & not) using mux2:1?
Q. Design and gate using 1:2 dmux?
Q. Flip-Flop convertions (ex: jk-d,d-t,t-jk like)?
Q. What is local-skew and global-skew?
Q. Skew is useful or drawback or both?
Q. Define glitch?
Q. Implement gate leval logic circuit to design frequency 3 divider
with 50% duty cycle(input clock duty is 50%)?
Q. Describe about metastability?
Q. Design inverter and buffer using xor gate?
Q. Build a 4:1 MUX using only 2:1 MUX?
Q. Design 2:4 decoder using 3:8 decoder?
Q. List out the differences between mealy and Moore state machine?
Q.Which is
having more states? show the block diagram of each?
Q. Difference between graycode, one hot and binary encoding?
Q. For power efficient designs which is better?
Q. Draw the FSM for pattern detector both over lapping and non overlapping
(101101)?
Q. Design a combinational circuit to detect all bits in the vector is
same (16-bit vector)?
Q. What advantage is 2’s compliment over 1’s complement?
Q. Implement 1-bit full-adder using 2:1mux’s?
Q. What is LUT in FPGA?
Q. Design a frequency 2 devider using JK Flip-Flop?
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