Reasoning Interview Questions

Q) Suppose you have a 3 liter jug and a 5 liter jug. The jugs have no measurement lines on them either. How could you measure exactly 4 liter using only those jugs and as much extra water as you need?

ANS :

Step 1 : First, fill the 5 liter jug and then pour it into the 3 liter jug. The 5 liter jug now has only 2 liters left.

Step 2 : Next, empty out the 3 liter jug. Then, pour the 2 liters from the 5 liter jug to the 3 liter jug. So, now the 3 liter jug has 2 liters.

Step 3 : Fill the 5 liter jug again, and pour 1 liter into the 3 liter jug. Now, what’s left in the 5 liter jug? Well, exactly 4 liters! There’s your answer.

Q) There are 3 baskets labeled ‘Apples’, ‘Oranges’ & ‘Mixture’. One of them contains only Apples, one only Oranges and  one has mix of apples and oranges both.

These baskets are not labeled correctly. In fact, the labels on these baskets always lie. (i.e. if the label says Oranges, Then you are sure the basket either has only Apples or Mixture).

You are allowed to pick one fruit from one basket (Not allowed to see other fruits), and you have to put all the labels correctly on the basis of that information (by seeing only one fruit from any one basket).

How will you do that ?

ANS:

Pick a fruit from the basket labeled ‘Mixture’. We know from the question that this basket does not contain ‘Mixture’ for sure.

1. If this fruit is an apple, then label this Basket as ‘Apple’ (Because this basket does not contain Mixture, so if one is apple, all are apples only). Now we’ve determined that the basket labeled as ‘Mixture’ only contains Apples.
2. If we look at the basket labeled as ‘Oranges’, we know that since the label is incorrect, this basket either has only apples in it or has Mixture. Since we already know which basket contains only apples, we know that the basket labeled as ‘Oranges’ contains ‘Mixture’. So label it as ‘Mixture’. The 3rd basket will be labeled as ‘Oranges’.

You can apply the same logic if you assume you initially picked an orange from the basket labeled as ‘Mixture’

Q) You have two sticks and matchbox. Each stick takes exactly an hour to burn from one end to the other. The sticks are not identical and do not burn at a constant rate. As a result, two equal lengths of the stick would not necessarily burn in the same amount of time.  How would you measure exactly 45 minutes by burning these sticks?

ANS: This puzzle used to be asked in Wall Street interviews long time ago. It is very rare for this question to be asked now but it is a very good question to help you think a little outside the normal thought process.

The answer is really simple. Since the sticks do not burn at a constant rate, we can not use the length of the stick as any sort of measurement of time. If we light a stick, it takes 60 minutes to burn completely. What if we light the stick from both sides? It will take exactly half the original time, i.e. 30 minutes to burn completely.

0 minutes – Light stick 1 on both sides and stick 2 on one side.
30 minutes – Stick 1 will be burnt out. Light the other end of stick 2.
45 minutes – Stick 2 will be burnt out.

For more Questions below are the references

http://www.programmerinterview.com/index.php/puzzles/measure-4-liters/

http://www.mytechinterviews.com/9-minutes

http://www.ritambhara.in/3-basket-puzzle-appleorange-puzzle/

Test your Verilog HDL...

Q. List out the difference between casex, casez and case statements?

Q. If a code having more than one $monitor does it work all the $monitors?

Q. Write a Verilog code for asynchronous reset D-Flip-Flop & synchronous reset D-Flip-Flop?

Q. Does delay can synthesizable if not can you give where do use?

Q. Do you know about User defined primitives?

Q. How do you generate clock in Verilog ?(write 2 or more logics)?

Q. List out the difference between casex, casez and case statements?

Q. If a code having more than one $monitor does it work all the $monitors?

Q. Write a Verilog code for asynchronous reset D-Flip-Flop & synchronous reset D-Flip-Flop?

Q. Does delay can synthesizable if not can you give where do use?

Q. Do you know about User defined primitives?

Q. How do you generate clock in Verilog ?(write 2 or more logics)?

Q. What is difference between force, freeze and deposit?

Q. What is the difference between reg and wire?

Q. Can we write assign inside procedural block (is it syntactically correct)?

Q. List out the differences between task and function?

Q. Difference between Asynchronous and Synchronous reset?

Q. How to you code it(Verilog)?

Q. Write a Verilog code for frequency 2 divider?

Q. Write a Verilog code for frequency 3 divider?(Use only single edges trigger mechanism)

Q. What is the difference between $display, $write and $monitor?

Q. List out the few differences between 1995 and 2001 Verilog standards?

Q. What is MCD in Verilog?

Q. What is the difference between transport delay and inertial delay?

Q. Is the following one is correct? If correct Why? (Reason)

            `timescale 1 ps/ 1 ns

Q. What values does the following operators return(===,==)?

Q. What are the differences between blocking and non-blocking assignments. Does always non-blocking assignment infer a Flip-Flop?

Q. In a following code which statement will work(WHy)?

       module logictest(input a,b,clk,output reg temp);

       always @(posedge clk)

       begin

        temp <= a&b;//-----------Statement 1

        temp <= a|b;//-----------Statement 2

       end

      endmodule

Q. Does delay can synthesizable if not can you give where do use?

Q. Do you know about User defined primitives?

Q. How do you generate clock in Verilog ?(write 2 or more logics)

Q. Does the following code infer a latch

always @ (b or c)

begin

a = 0;

if (b) begin

d = c;

end
Q. What is meant by latch inferring ,how do you avoid it in design?
Q.  How many times does the following repeat loop will execute? 

begin

a = 1;

repeat (a)

a= b + 1;

end 

Q. Is the following statement is correct?

       reg [-1:5] x; 

Q. how can you pass real values through ports? 

Q. Maximum how many number files can be opened using fopen?

Q. Is it possible to disable a function, task, named block?

Q. What is delta simulation time?

Q.  Difference between && and &, if any?

Q.  What is the difference between $finish and $stop ?

Q.  What are the timing controls in Verilog?

Q. What is $strobe in Verilog?