Vlsi Terminology

Multiplexer with Interview questions

Multiplexer:

Multiplexer is also known as Data Selector  or Mux or mux.

Mux represents minterms of input to output  ratio 2^n:1. Here  2^n is inputs  and n is select lines.

Ex:  1. 2:1 Mux =>  Ratio= 2^1:1 , Select lines =1 , Inputs=2, output=1

       2. 4:1 Mux =>  Ratio= 2^2:1 , Select lines =2, Inputs=4,output=1

       3. 8:1 Mux =>  Ratio= 2^3:1 , Select lines =3, Inputs=8,output=1

       4. 16:1 Mux =>  Ratio= 2^4:1 , Select lines=4, Inputs=16,output=1

Mux symbol: for 2:1 Mux :

Basic Gates with Interview Quesions

Q. Using two xor gates design as buffer and as inverter?

ANS:

keep A=0 ,B value vary Xor gate  will work as Buffer

  keep A=1 ,B value vary  Xor gate will work as Inverter

Q. How many 2 input XOR gates required implementing 16-bit parity generator?

ANS: Design n-bit Parity Generator using 2-input Xor gate require: (n-1) Inputs .So, 16-bit parity generator require 15  2-input Xor gates.

VLSI design levels....

Clock Domains Crossing Issues

Clock Domain Crossing

In today’s complex system on chip (SoC) designs, different blocks are operating at different frequencies.if suppose a signal is travelling from one clock domain to another some problems are occur which are  setup and hold violation, metastability and unreliable data transfers(data loss, data in coherency), CDC may occur when a signal is travelling from one block to another block which are operating at same frequency and their phases are not same.

To avoid this CDC issues there are some methods to solve:

• Handshake Signaling method.
• Asynchronous FIFO.

Simple Verilog code for single bit Clock Domain Crossing:

module clk_2_cross ( rst_n,clk1, clk2,d_in, d_out);

input rst_n;

//--------------------------input clk1;

input clk2;

input  d_in;

output d_out;

reg [7:0] data_out_meta;

reg [7:0] data_out_reg;

reg [7:0] data_out_reg_r;

wire[7:0] data_out;

// Always block to Synchronize the signal

always @ (posedge clk2 or negedge rst_n)

begin

 if (! rst_n)

  begin

     d_in1 <= 'b0;

     d_in2 <= 'b0;

 end

else

begin

  d_in1 <= d_in;

  d_in2 <= d_in1;

end

assign d_out = d_in2;

end

endmodule

Above code infers the following digital circuit.

For More Knowledge on this topics go to the Following links

          http://www.eetimes.com/document.asp?doc_id=1279906

          http://www.asic-world.com/tidbits/clock_domain.html

Difference between Latch & Flipflop

Verilog Best Learning Books

S.No.	Title Name	Authors
1	Verilog LRM	IEEE
2	The Verilog Hardware Description Language	Thomas, D.E . Moorby, Philip R .
3	A Verilog HDL Primer	A Verilog HDL Primer
4	Verilog HDL : A Guide to Digital Design and Synthesis	Samir Palnitkar
5	Verilog -- 2001: A Guide to the New Features of the Verilog Hardware Description Language	Stuart Sutherland
6	Starter'S Guide To Verilog 2001	Michael D.Ciletti
7	HDL Chip Design : A Practical guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog	Douglas J. Smith
8	The Verilog Pli Handbook	Stuart Sutherland
9	Verilog HDL Synthesis, A Practical Primer	J. Bhasker
10	Verilog Quickstart	James M. Lee
11	Real Chip Design and Verification Using Verilog and VHDL	Ben Cohen
12	Verilog Designer's Library	Bob Zeidman
13	The Complete Verilog Book	Vivek Sagdeo
14	Principles of Verilog PLI	Swapnajit Mittra
15	Analog Behavioral Modeling with the Verilog-A Language	Dan FitzPatrick

Verilog Reserved Words (key words)...

always	: starts an always begin ... end sequential code block
and	: gate primitive
assign	: parallel continuous assignment
automatic	: a function attribute, basically reentrant and recursive
begin	: starts a block that ends with  end (no semicolon)
buf	: gate primitive, buffer
bufif0	: gate primitive, buffer if control==0
bufif1	: gate primitive, buffer if control==1
case	: starts a case statement
casex	: starts a case statement where x matches
casez	: starts a case statement where z matches
cell	: library, cell identifier, in configuration
cmos	: switch primitive, cmos
config	: starts a configuration
deassign	: stops the corresponding  assign  from accepting new values
default	: optional last clause in a case statement
defparam	: used to over-ride parameter values
design	: top level module, in configuration
disable	: a task or block
endmodule	: end of a module definition
endprimitive	: end of a primitive definition
endspecify	: end of a specify
endtable	: end of a table definition
endtask	: end of a task definition
event	: data type
for	: starts a for statement
force	: starts net or variable assignment
forever	: starts a loop statement
fork	: begin parallel execution of sequential code
function	: starts a function definition
generate	: starts a generate block
genvar	: defines a generate variable
highz0	: drive strength 0
highz1	: drive strength 0
if	: starts an  if  statement, if(condition) ...
incdir	: state dependent path declaration
include	: file path for library
initial	: Include the file inspection
inout	: starts an initial begin ... end sequential block
input	: declares a port name to be both input and output
instance	: declares a port name to be input
integer	: specify instance name, in configuration
join	: variable data type, 32 bit integer
large	: end of a parallel fork
liblist	: library search order for modules, in configuration
library	: location of modules, libraries and files
localparam	:  starts a local parameter statement, not over-ridden
macromodule	: same as module with possibly extra meanings
medium	: charge strength, 2, of trireg
module	: begin a module definition, also called a cell or component
nand	: gate primitive, nand
negedge	: event expression, negative edge
nmos	: switch primitive, nmos
nor	: gate primitive, nor
noshowcancelled	: no report trailing edge precedes leading edge, in specify
not	: gate primitive, not
notif0	: gate primitive, not if control==0
notif1	: gate primitive, not if control==1
or	: gate primitive, or
output	: declares a port name to be an output
parameter	: starts a parameter statement
pmos	: switch primitive, pmos
primitive	: event expression, positive edge
posedge	: starts the definition of a primitive module
pull0	: drive strength 5
pull1	: drive strength 5
pulldown	: gate primitive
pulsestyle_onevent	: glitch detection, in specify
real	: variable data type, implementation defined floating point
realtime	: variable data type, floating point time
reg	: variable data type, starts a declaration of name(s)
release	: release a forced net or variable assignment
remos	: switch primitive, remos
repeat	: starts a loop statement
rnmos	: switch primitive, rnmos
rpmos	: switch primitive, rpmos
rtran	: bidirectional switch primitive, rtran
rtranif0	: bidirectional switch primitive, rtranif0
rtranif1	: bidirectional switch primitive, rtranif1
scalared	: property of a vector type
showcancelled	: report trailing edge precedes leading edge, in specify
signed	: type modifier, reg signed
small	: charge strength, 1,  of trireg
specify	: starts a specify block
specparam	: starts a parameter statement for timing delays
strong0	: drive strength 6
strong1	: drive strength 6
supply0	: net data type, and drive strength 7
supply1	: net data type, and drive strength 7
table	: start a table definition in a primitive
task	: starts a task definition
time	: variable data type, 64 bit integer
tran	: bidirectional switch primitive, tran
tranif0	: bidirectional switch primitive, tranif0
tranif1	: bidirectional switch primitive, tranif1
tri	: net data type
tri0	: net data type, connected to VSS
tri1	: net data type, connected to VDD
triand	: net data type, tri state wired and
trior	: net data type, tri state wired or
trireg	: register data type associates capacitance to the net
unsigned	: type modifier, unsigned
use	: library, cell identifier, in configuration
vectored	: property of a vector type
wait	: starts a wait statement
wand	: net data type, wired and
weak0	: drive strength 3
weak1	: drive strength 3
while	: starts a sequential looping statement, while(condition)
wire	: net data type, a basic wire connection
wor	: net data type, wired or
xnor	: gate primitive, xnor not of exclusive or
xor	: gate primitive, xor exclusive or