Synthesis Introduction

It is a Process of translating higher level RTL Description to low level Gate Level Description. 

“The process of parsing, translating, optimizing, and mapping RTL code into a specified standard cell  library.”

  

  

Synthesis produces registers and combinational logic at the RTL level. 

There are 4 timing paths in a chip:

1.       Input to reg path

2.       Reg to reg path

3.       Reg to output path

4.       Input to output path

Some of the tools

Logic synthesis tools for ASICs:

1. Design Compiler by Synopsis

2. RTL Compiler by Cadence

3. BlastCreate by Magma

For FPGA’s:

          1. XST by Xilinx