Core VLSI: September 2014

MAHENDRA AND SATYAM INTERVIEW QUESTION

1. What is Synthesis?

2. Difference between int and integer.

3. Difference between bit [7:0] and byte.

4. Significance of logic.

5. Advantage of dynamic array.

6. Difference between dynamic array, queue and associative array.

7. Difference between verilog and systemverilog.

8. What is static and dynamic?

9. Why can’t we use interface instead mailbox?

10. What is callback?

11. What is casting? How it works?

12. Explain polymorphism with an example.

13. What is encapsulation?

14. Question regarding stratified event queue how blocking and non-blocking assignments happens in verilog.

15. Simplify the equation x' + xy.

16. Design xor gate using muxes.

17. What is the use of modports?

18. What is input clock skew and output clock skew?

19. Difference between function and task.

20. How to randomize a variable though it is not declared as rand/randc?

21. How this array works arry [*] [$] [ ].

22. Explain Driver code for RAM.

23. Explain function new and super.build in UVM.

24. Connect virtual interface in driver build_phase.

25. Explain config_db and resource_db.

26. Explain report phase in UVM.

27. features of SV.

28. What is the limitation of randc?

29. Declaring a variable as rand, how to make use of that variable to work as randc.

30. Explain about ignore bins.

31. Explain code coverage.

32. Explain raise objection.

33. Explain global stop request.

34. Difference between Mealy and Moore fsm.

35. Design an fsm for sequence detector 1001.

36. Difference between object and component.

37. Difference between TLM 1.0 and TLM 2.0

Other Questions :

1. A ring counter having 10 pulses .how many flip-flops needed ?

2. How many minimum number of gates required to implement Half adder ?

3. tp =10ns,ts=6ns,th=2ns, calculate clock frequency.

4. Difference between task and function ? option given.

5. Difference between Final and Initial block ? option given.

6. Difference between Latch and Flip-Flops ? option given.

7. Difference between Create() and New() .

8. Find the minimum nu. of transistor required to implement f= A(BC+BDE).Using CMOS

9. FIFO depth calculation.

10. Which gate is required to implement 4:16 decoder using two 3:8 decoder?

a) AND b) XOR c) NOT d) OR e) All of them

11. NAND gate will be ..........gate .if it uses -ve logic .

12. Which statement will be execute in the below piece of code

casex(3’b110)

3’bxx1 : statement 1;

3’bx1x : statement 2;

3’b1xx : statement 3;

default : statement 4;

endcase

13.

module test;

reg x,y ;

reg [1:0] z;

initial

begin

fork

x =1’b0;

y =1’b1;

z ={y,x};

join

end

endmodule

what should be the value of z in the above piece of code ?

14. In which of the following options callback can be always used

a) Driver

b) Scoreboard

c) Agent

d) Mailbox

16. What is the value of “C” , if q = 1’bx in the below code

module test;

reg [1:0] a, b;

reg q;

wire[1:0] c ;

assign c =(q)?a:b;

initial begin

a=2’b10; b=2’01;

end

endmodule

17. always@(posedge clk or negedge reset)

begin

if(reset)

Q <= 1;

else

Q<=0 ;

End

Which option is suitable for the above piece of code

a) Asynchronous reset

b) Synchronous reset

c) Asynchronous set

d) Synchronous set

18. Which is not related to the race around condition?

a) Clocking block

b) Program block

c) Non-blocking

d) Mailbox

e) All of the above

19. How many address lines are required to address 256*8 memory?

20. Two Mod 16 counter connected back to back 1^st is synchronous & 2^nd is ripple counter .

If each flip flop have propagation delay tp then what is the propagation delay of full circuit.

21. Which statement in the following code is wrong?

Class abc ;

Integer abc_var ;

endclass

class cde extends abc ;

integer abc_var ;

endclass

program test();

abc abc_obj ,abc_obj1 ;

cde cde_obj , cde_obj1 ;

abc_obj1 = new();

cde_obj = abc_obj1 ;

cde_obj1 = new();

abc_obj = cde_obj1;

endprogram

22. What type is a Microcontroller?

a) ASIC

b) CPLD

c) FPGA

d) ASSP

e) ISSP

Mobiveil Interview Questions

1) What is functional coverage and code coverage?

2) What is inheritance and polymorphism?

3) Questions related to SVA.

4) Verification flow for VMM and UVM.

5) Difference between OVM and UVM.

6) Questions related to SPI and UART project.

7) Draw verification environment in UVM.

8) Explain the different testcases and scenario to verify the following specification

Consider a block with four 32 bit input channel and four 32 bit output channel, where as input channel are non blocking and each output channel with its own address individually. A packet of data can be forwarded through any one of the input channel or in parallel manner. Packet consist of header, payload and crc bytes.

9) Draw the verification environment in UVM.

10) Write down the code for transaction, driver, monitor for the above scenario.

11) Explain about the scoreboard needs for the above scenario.

12) How will you connect your driver & sequencer and where.

13) What is TLM?

14) Difference between TLM 1.0 and TLM 2.0

15) What is automation in UVM and its purpose?

16) What is configuration database and configuration object.

17) What is overriding in UVM and give some examples.

18) How will you connect your virtual interface in UVM environment.

19) How you will collect data to scoreboard and from where.

20) Explain about VMM and its flow.

21) How you will change static interface to dynamic interface.

22) Difference between for join and begin end.

23) Explain about UDP and FEC coverage.

24) Explain about coverage exclusion.

25) Explain about reusable environment in UVM.

26) Advantages and disadvantages of macros in UVM.

Synopsys Interview Questions

1)Draw the testbench architechture of UVM and Explain.

2)Advantages of UVM over VMM.

3)What is the use of callbacks?

4)Explain a scenario which we need callbacks.

5)What is factory class?

6)How can we override transaction class in UVM and VMM?

7)While overriding how the handle assignment is woking in factory?

8)How to randomize transaction class in sequence?

9)How to find the depth of analysis fifo?

10)Explain about configdb in UVM.

11)How config db is working in UVM?

12)How to map static and virtual interface using config db?

13)Write the code for the above mentioned scenario.

Interview Questions of Sandisk and PerfectVIP Technologies

Written Test

1) Percentage Aptitude.

2) Geometry –triangle Aptitude.

3) Logical reasoning.

4) Sequence detection (2’s complement).

5) Cubes Aptitude.

6) Propagation delay.

7) Flip-flop.

8) Mux.

9) FSM.

10) Number systems Aptitude.

11) Analog keyboard switch.

12) Glitches.

13) Setup and hold time.

14) Counters.

Technical Interview

Round-1

1) What is Synchronous and Asynchronous devices and its type.

Note:- Combinational circuit is asynchronous

2) Different between latch and flip flop.

3) Why do you prefer System Verilog.ie., Advantages of system verilog over verilog.

Round-2

4) Project flow and its details.

5) Body effect and CMOS circuit connections.

6) Types of encoding and which is the more advantage to use.

7) Which one is more preferred in circuit design. NAND or NOR.

Note:- input capacitance.

8) Types of canonical form, which is preferred.

9) Sensitivity list.

10) Dual port RAM.

11) Propagation delay.

12) Explain Setup and Hold time with waveform example.

i) Violations

ii) How to prevent set and hold time violations.

13) Draw frequency divide by 3 circuit and its waveform.

14) What is inertial delay.

15) Explain callbacks.

16) What is TLM?

17) Draw UVM flow diagram and explain about the different phases.

18) What is the advantage of UVM over System verilog.

19) Determine the output for the given programs which contains function, task and inheritance.

20) Write system verilog verification environment to verify FIFO module.

Specification details:-

Clk_read -10 MHz

Delay - 2 cycle

Total capacity of burst-100 bytes [burst_width]

Clk_write – 15 MHz

Delay – 1cycle

Flags - empty,full

21) TB architecture for SV and explain each blocks and stages.

22) Explain the following terms

i) Polymorphism

ii) Inheritance

iii) Clocking block

iv) Modport

v) Interface

Round-3

23) Types of FSM, which type is implemented in your project.

24) Is Ts and Th calculated for combinational circuits and gates.

25) What is meta stability?

26) What is verbosity?

List of EDA Companies and their tools for ASIC and FPGA
Industrial Tool List
Cadence
Allegro AMS Simulator	Incisive Debug Analyzer
Allegro Design Workbench	Incisive Enterprise Simulator
Allegro FPGA System Planner	InCyte Chip Estimator
Allegro Package Designer	NanoRoute Router
Allegro Package SI	OrCAD PCB Designer
Allegro PCB Designer	OrCAD Signal Explorer
Allegro PCB SI	Physical Verification System
Assura Physical Verification	PSpice A/D and Advanced Analysis
Cadence Chip Optimizer	Quantus QRC Extraction Solution
Cadence Chip Planning System	QuickView Signoff Data Analysis Environment
Cadence Incisive Verification Kit	QuickView Signoff Data Analysis Environment
Cadence InCyte Chip Estimator	Sigrity BroadBand Spice
Cadence MaskCompose Reticle and Wafer Synthesis Suite	Sigrity OptimizePI
Cadence OrCAD Capture / Capture CIS	Sigrity PowerSI
Cadence OrCAD FPGA System Planner	Sigrity SystemSI
Cadence OrCAD PCB Designer	SiP Digital Architect
Cadence Space-Based Router	SiP Digital Layout
Chip Optimizer	SoC Encounter RTL-to-GDSII System
Chip Planning System	Space-Based Router
C-to-Silicon Compiler	Spectre Accelerated Parallel Simulator
Encounter Conformal Constraint Designer	Spectre Circuit Simulator
Encounter Conformal ECO Designer	Spectre eXtensive Partitioning Simulator
Encounter Conformal Equivalence Checker	Spectre RF Simulation
Encounter Conformal Low Power	Virtuoso Analog Design Environment
Encounter DFT Architect	Virtuoso Chip Assembly Router
Encounter Digital Implementation System	Virtuoso Digital Implementation
Encounter Power System	Virtuoso Layout Suite
Encounter RTL Compiler	Virtuoso Power System
Encounter RTL Compiler Advanced Physical Option	Virtuoso Schematic Editor
Encounter Timing System	Virtuoso UltraSim Full-Chip Simulator
Encounter True-Time ATPG	Virtuoso Visualization and Analysis
First Encounter Design Exploration and Prototyping	VoltageStorm Power Verification
Synopsis
Circuit Check	Power Compiler
coreAssembler	PrimeRail
coreBuilder	PrimeTime
Custom Designer LE	PrimeYield
Custom Designer SDL	Liberty NCX
Custom Designer SE	LightTools
Custom WaveView	MVRC Multi-voltage Rule Checker
CustomExplorer	MVSIM
CustomSim	NanoTime
Formality	Pioneer-NTB with Vera
FPGA-Based Prototyping	Platform Architect
Helix	Power Compiler
Hercules	PrimeRail
HSIM	PrimeTime
HSPICE	PrimeYield
IC Compiler	Liberty NCX
IC Compiler II	LightTools
IC Validator	Lynx Design System
IC Workbench Plus	Liberty NCX
Innovator	LightTools
Interconnect Simulation	Logic Libraries
Laker Custom Design	Lynx Design System
Laker Flat Panel Display
Laker Test Chip Development	Memory Test and Repair
Leda	minPower Components
Liberty NCX	ICanalyst
LightTools	Model sim
Logic Libraries	Olympus-SoC
Lynx Design System	Pyxis Implement
NanoTime	Pyxis Layout
Odyssey	Pyxis Schematic
Platform Architect	Questa Sim

XILINX

Vivado Design Suite
ISE Design Suite

Mentor graphics

Calibre CMPAnalyzer	calibre xRC
Calibre nmDRC	calibre Yield Analyzer
Calibre PERC	Eldo Premier
calibre nmLVS

Core VLSI

Tuesday, September 23, 2014

Reset: a synchronous or an asynchronous reset is useful in design?

Monday, September 15, 2014

Verilog and System Verilog Interview Questions

Tuesday, September 9, 2014

List of EDA Companies and their tools for ASIC and FPGA

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