Verilog synthesizable and non-synthesizable constructs

•      Verilog allows several ways to describe one thing, Synthesis tools often require only a limited subset of constructs;

•       Example: R

•      Registers and Flip Flops must be described in a certain way;

#	Construct	About	Synthesizability
1	Initial	Typically for test benches	No
2	Primitives	Only Verilog primitives are synthesizable, where as UDP’s are not	No
3	Assign and De assign	Assign and deassign of reg data types is not supported for synthesis. But assign on wire data type is supported.	No for reg, Yes for wire
4	Force and Release	Not supported for synthesis, they are test bench constructs	No
5	Fork and Join	Not supported for synthesis	No
6	Delays	Normally #10 Even if written in design, synthesis tool will ignore it during simulation.	No
7	Real	Not supported for synthesis	No
8	Time	Not supported for synthesis	No
9	Ports	Input, output, inout will synthesizable(use inout at top level)	Yes
10	Parameters	This makes design more generic, synthesizable	Yes
11	Modules	The body of the code containing declarations and the logic	Yes
12	Instantiation	If the module is synthesizable construct’s instance will also be synthesizable	Yes
13	Function and Tasks	Both will be synthesizable(when task has no timing constructs)	Yes
14	always	A procedural block, with sensitivity list, and reg type in LHS of expressions	Yes
15	Loops	For loop is synthesizable
16	*,/,+,-,%,!,&&,||,>,>=,<=,<,&,!=,==,~&,|,~|,^,^~,~^,<<,>>,{},?	Operators – arithmetic (unary and binary), logical, bitwise, relational, reduction (unary)	Yes
17	Compiler directives (`define, `ifdef, `undef etc..)	Supports for synthesis	Yes
18	Assignments(blocking and non blocking)(=,<=)	Supports for synthesis	Yes
19	Bits and part selects	Supports for synthesis	Yes
20	If - else, case, casex, casez	Supports for synthesis	Yes
21	Disable	Partial