Clock Divider Implementations

References:

                            http://www.slideshare.net/DeepakFloria/divide-by-n-clock



In this post first explain even number clock dividers next odd number clock dividers after you can find the references.


Divide by-2 clock:

//Design module divide_by_2(rst_n,clk,gen_by2_clk);   input rst_n;   input clk;   output gen_by2_clk;     reg reg1;     always @ (posedge clk,negedge rst_n)   begin   if(!rst_n)     begin       reg1 <= 1'b0;     end   else     begin       reg1 <= ~reg1;     end   end       assign gen_by2_clk = reg1; endmodule

//Test Bench `timescale 1ns/1ns module tb_divide_by_2; reg rst_n; reg clk; wire gen_by2_clk; divide_by_2 U1(rst_n,clk,gen_by2_clk); initial begin   clk = 1'b0;   forever begin   #1;   clk = ~clk;   end end initial begin   rst_n = 1'b0;   #2;   rst_n = 1'b1;   #100;   $finish; end endmodule

Divide by-4 clock:

//Design module divide_by_4(rst_n,clk,gen_by4_clk);   input rst_n;   input clk;   output gen_by4_clk;     reg [1:0]reg1;     always @ (posedge clk,negedge rst_n)   begin   if(!rst_n)     begin       reg1 <= 2'b00;     end   else     begin       reg1 <= reg1 + 1'b1;     end   end       assign gen_by4_clk = reg1[1]; endmodule

//Test Bench `timescale 1ns/1ns module tb_divide_by_4; reg rst_n; reg clk; wire gen_by4_clk; divide_by_4 U1(rst_n,clk,gen_by4_clk); initial begin   clk = 1'b0;   forever begin   #1;   clk = ~clk;   end end initial begin   rst_n = 1'b0;   #2;   rst_n = 1'b1;   #100;   $finish; end endmodule