Clock Divider Implementations

References:

                            http://www.slideshare.net/DeepakFloria/divide-by-n-clock



In this post first explain even number clock dividers next odd number clock dividers after you can find the references.


Divide by-2 clock:

//Design module divide_by_2(rst_n,clk,gen_by2_clk);   input rst_n;   input clk;   output gen_by2_clk;     reg reg1;     always @ (posedge clk,negedge rst_n)   begin   if(!rst_n)     begin       reg1 <= 1'b0;     end   else     begin       reg1 <= ~reg1;     end   end       assign gen_by2_clk = reg1; endmodule

//Test Bench `timescale 1ns/1ns module tb_divide_by_2; reg rst_n; reg clk; wire gen_by2_clk; divide_by_2 U1(rst_n,clk,gen_by2_clk); initial begin   clk = 1'b0;   forever begin   #1;   clk = ~clk;   end end initial begin   rst_n = 1'b0;   #2;   rst_n = 1'b1;   #100;   $finish; end endmodule

Divide by-4 clock:

//Design module divide_by_4(rst_n,clk,gen_by4_clk);   input rst_n;   input clk;   output gen_by4_clk;     reg [1:0]reg1;     always @ (posedge clk,negedge rst_n)   begin   if(!rst_n)     begin       reg1 <= 2'b00;     end   else     begin       reg1 <= reg1 + 1'b1;     end   end       assign gen_by4_clk = reg1[1]; endmodule

//Test Bench `timescale 1ns/1ns module tb_divide_by_4; reg rst_n; reg clk; wire gen_by4_clk; divide_by_4 U1(rst_n,clk,gen_by4_clk); initial begin   clk = 1'b0;   forever begin   #1;   clk = ~clk;   end end initial begin   rst_n = 1'b0;   #2;   rst_n = 1'b1;   #100;   $finish; end endmodule

FPGA Interview Questions

Q. What is FPGA?

ANS: Field Programmable Gate Array is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects.

Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.

Q. What are DCM’s? Why they are used?

ANS: Digital clock manager (DCM) is a fully digital control system that uses feedback to maintain clock signal characteristics with a high degree of precision despite normal variations in operating temperature and voltage. That is clock output of DCM is stable over wide range of temperature and voltage, and also skew associated with DCM is minimal and all phases of input clock can be  obtained . The output of DCM coming from global buffer can handle more load.

Q. What are the differences between FPGA and CPLD?

ANS:

FPGA:

A) SRAM based technology.

B) Segmented connection between elements.

C) Usually used for complex logic circuits.

D) Must be reprogrammed once the power is off.

E) Costly

CPLD:

A) Flash or EPROM based technology.

B) Continuous connection between elements.

C) Usually used for simpler or moderately complex logic circuits.

D) Need not be reprogrammed once the power is off.

E) Cheaper

Q. What is DFT ?

ANS: DFT means design for testability. 'Design for Test or Testability' - a methodology that ensures a design works properly after manufacturing, which later facilitates the failure analysis and false product/piece detection Other than the functional logic, you need to add some DFT logic in your design. This will help you in testing the chip for manufacturing defects after it come from fab.  Scan, MBIST, LBIST, IDDQ testing etc. are all part of this. (This is a hot field and with lots of opportunities)

Q. What is Synthesis?

ANS: Synthesis is the stage in the design flow, which is concerned with translating your Verilog code into gates - and that's putting it very simply! First of all, the Verilog must be written in a particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.

Q. What is slice? What is CLB?

ANS: The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits. CLB are configurable logic blocks and can be configured to combo, ram or rom depending on coding style CLB consist of 4 slices and each slice consist of two 4-input LUT (look up table) F-LUT and G-LUT. The memory assignment is a clocked behavioural assignment, Reads from the memory are asynchronous, and all the address lines are shared by the read and write statements.

Q. Can a CLB configured as ram?

ANS: Yes

Q. What is the purpose of DRC?

ANS: DRC is used to check whether the particular schematic and corresponding layout (especially the mask sets involved) cater to a pre-defined rule set depending on the technology used to design. They are parameters set aside by the concerned semiconductor manufacturer with respect to how the masks should be placed, connected, routed keeping in mind that variations in the fab process does not effect normal functionality. It usually denotes the minimum allowable configuration.

Q. Compare PLL & DLL?

PLL:

PLLs have disadvantages that make their use in high-speed designs problematic, particularly when both high performance and high reliability are required. The PLL voltage-controlled oscillator (VCO) is the greatest source of problems. Variations in temperature, supply voltage, and manufacturing process affect the stability and operating performance of PLLs.

DLLs, these however, are immune to these problems. A DLL in its simplest form inserts a variable delay line between the external clock and the internal clock. The clock tree distributes the clock to all registers and then back to the feedback pin of the DLL. The control circuit of the DLL adjusts the delays so that the rising edges of the feedback clock align with the input clock. Once the edges of the clocks are aligned, the DLL is locked, and both the input buffer delay and the clock skew are reduced to zero.

Advantages:

· Precision

· Stability

· Power management

· Noise sensitivity

· Jitter performance.

Q. What is LVs and why do we do that. What is the difference between LVS and DRC?

ANS: The layout must be drawn according to certain strict design rules. DRC helps in layout of the designs by checking if the layout is abide by those rules. After the layout is complete we extract the netlist. LVS compares the netlist extracted from the layout with the schematic to ensure that the layout is an identical match to the cell schematic.

Q. Can you suggest some ways to increase clock frequency?

ANS:

· Check critical path and optimize it.

· Add more timing constraints (over constrain).

· Pipeline the architecture to the max possible extent keeping in mind latency req's.

Q. What is the significance of FPGAs in modern day electronics?

ANS:

·         Less time to Market when comparing with ASIC

·         It’s better for start-up companies to design their projects using FPGA Rather than ASIC side

·         Less Cost and Reconfigurable As many require number of times

Q. FPGA design flow?

ANS:

                

Q. Tell me some features of FPGA you are currently using?

1.        FPGA Spartan3E:  (XC3S500E)

The Spartan 3E Starter Board provides a powerful and highly advanced self-contained development platform for designs targeting the Spartan 3E FPGA from Xilinx.

It features a 500K gate Spartan 3E FPGA with a 32 bit RISC processor and DDR interfaces.

The board also features

A Xilinx Platform Flash, USB and JTAG parallel programming interfaces with numerous FPGA configuration options via the onboard Intel StrataFlash and ST Microelectronics Serial Flash.

The board with a power supply and USB cable for programming so designs can be implemented immediately with no hidden costs.

The Spartan 3E Starter board is also compatible with the Micro Blaze Embedded Development Kit (EDK) and Pico Blaze from Xilinx.

2.    FPGA Spartan6: (XC6LX16-CS324)

The system development platform features Xilinx's newest Spartan-6 FPGA, 48Mbytes of external memory (including two non-volatile phase-change memories from Micron), and enough I/O devices and ports to host a wide variety of digital systems.

The on-board high-speed USB2 port provides board power, FPGA programming, and user-data transfers at rates up to 38Mbytes/sec.

A large collection of low-cost peripheral boards, including more than 30 Pmods and several new Vmods, can add additional features to the Nexys3,

 Including A/D and D/A converters, breadboards, motor drivers, displays, etc. The Nexys3 is fully compatible with all Xilinx tools, including the free  Chipscop, EDK (embedded processor design kit) and other tools.

Q. What is LUT?

 Look up Table:

·            Look-up tables (LUTs) are used to implement function generators in CLBs.

·            Four independent inputs are provided to each of two function generators                (F1-F4 and G1-G4).

·            These function generators can implement any arbitrarily defined Boolean function of four inputs.

Q. How to generate clocks on FPGA?

·         you need clock source regardless to drive FPGA ,

·         inside you can use PLL to generate specific frequencies.

·         Also you can use counters to scale down clock

Q. What are FPGA Editor File formats?

          FPGA Editor Reads and writes the following file types:

File Type	Input / Output	Definition
NCD	Input/Output	MAP or PAR generates the .ncd file. FPGA Editor uses this file with the New or Open command from the File menu.  You can edit the NCD file in the FPGA Editor.
PCF	Input/Output	A .pcf file is an ASCII file containing physical constraints created by the MAP program as well as physical constraints entered by you. You can edit the PCF file in the FPGA Editor.
NMC	Input/Output	An .nmc file contains a physical hard macro which can be created or viewed with the FPGA Editor.
ELF	Input	An .elf file (pronounced “elf”) is a binary data file that contains an executable CPU code image, ready for running on a CPU
DRF	Input	A .drf file (pronounced “dwarf”) is a binary data file that also contains the executable CPU code image, plus debug information required by symbolic source-level debuggers.
MEM	Input	A .mem file (memory) is a simple text file that describes contiguous blocks of data.
BIT	Output	A .bit file contains location information for logic on a device, including the placement of CLBs, IOBs, TBUFs, pins, and routing elements. The bitstream also includes empty placeholders that are filled with the logical states sent by the device during a readback. Only the memory elements, such as flip-flops, RAMs, and CLB outputs, are mapped to these placeholders, because their contents are likely to change from one state to another. When downloaded to a device, a bitstream configures the logic of a device and programs the device so that the states of that device can be read back.
CDC	Output	A .cdc file can be generated from the ILA command.

Q. How do you implement DCM?

the manual of my spatran 3E fpga kit says Alternatively, use the FPGA’s Digital Clock Manager (DCM) to generate or synthesize other frequencies from the on-board 50 MHz oscillator.

Q. Why is map-timing option used?

To improve design performance, timing, and packing for highly utilized designs.

Q. What are different types of timing verifications?

1.      Static timing:	2.      Dynamic timing:
a. The delays over all paths are added up.	a. The design is simulated in full timing mode.
b. All possibilities, including false paths, verified without the need for test vectors.	b. Not all possibilities tested as it is dependent on the input test vectors.
c. Much faster than simulations, hours as opposed to days.	c. Simulations in full timing mode are slow and require a lot of memory.
d. Not good with asynchronous interfaces or interfaces between different timing domains.	d. Best method to check asynchronous interfaces or interfaces between different timing domains.